1. Field of the Invention
The present invention relates to a clock phase correction circuit for a semiconductor memory device. More particularly, it relates to a clock phase correction circuit which reduces in advance all lock ranges by using a half-mixer to a conventional delay locked loop (hereinafter referred to as a DLL) circuit, and thus generates a clock signal having a fast lock time and a very small jitter.
2. Description of the Prior Art
In recent times, to solve a problem of a data set-up time and a data hold time, a clock phase correction circuit has been widely used to a high-speed synchronous dynamic random access memory (SDRAM), a rambus DRAM, a synclink DRAM, and a double data rate SDRAM, etc.
Generally, as a digital system's speed becomes faster, a phase locked loop (hereinafter referred to as a PLL) circuit or a DLL circuit has been employed to remove a skew or to eliminate the phase difference between an external clock Extclk and an internal clock Intclk.
The reason why the PLL circuit or DLL circuit is used will be described below.
A first reason is that a load of clock inside of a chip increases and a delay of a clock driver increases if a degree of integration of an integrated circuit becomes higher.
In this way, if the delay of the clock driver increases, a set-up time and a hold time increases, and a design of a system having a high operation frequency is restricted. At this time, a skew in the clock driver can be removed by using an on-chip PLL.
A second reason is that a clock being input to most chips cannot ensure a duty cycle of 50% although many circuits require the duty cycle of 50%. Therefore, to ensure the duty cycle of 50%, the circuits receive an external clock having a double frequency as compared with an internal clock's frequency, divide the external clock, and then use it.
In this case, there is a shortcoming that a frequency of the external clock Extclk increases, thus the PLL circuit should be employed to ensure the duty cycle.
A third reason is that a microprocessor is generally operated at a frequency higher than that of the external clock Extclk. This is very profitable to a system design. At this time, if the PLL circuit is employed to the system design, an internal clock having a frequency higher than the external clock's frequency can be produced.
The present invention relates to a DLL circuit.
The DLL circuit makes a coincident phase between the external clock Extclk and he internal clock Intclk. FIG. 1 is a block diagram of a conventional DLL circuit.
As shown in FIG. 1, the conventional DLL circuit includes:
a phase detector 30 for detecting a phase difference between an external clock Extclk and a feedback clock Fbclk; PA1 a controller 20 which receives an output signal of the phase detector 30 as input, and controls a delay means 10; PA1 a delay means 10 which receives a control signal from the controller 20 as input, and adjusts a delay; and PA1 a model portion 40 for modeling a real physical delay.
The controller 20 can be differently constructed according to the type of the delay means 10.
FIG. 2 is a block diagram of a DLL circuit in which a counter 22 and a digital-to-analog converter 21 are used as a controller 20 in the case of an analog-type delay means 10.
FIG. 3 a block diagram of a DLL circuit in which an electric charge pump 23 is used as a controller 20 in the case of an analog-type delay means 10.
FIG. 4 is a block diagram of a DLL circuit in which a counter 22 and a selector 24 are used as a controller 20 in the case of a digital-type delay means 10.
Referring to FIGS. 2-3, in case of an analog-type delay means, the controller 20 can be constructed as a digital-to-analog converter 21 and a counter 22 or as an electric charge pump 23. In case of a digital-type delay means, as shown in FIG. 4, the controller 20 can be constructed as a selector 24 and a counter 22.
In operation of the conventional DLL circuit of FIG. 1, the phase detector 30 detects a phase difference between an external clock Extclk and a feedback clock Fbclk via the model portion 40 and transmits a high or low signal to the controller 20.
The controller 20 receives the high or low signal generated from the phase detector 30 and controls the delay means 10. A delay time of the delay means 10 is controlled by an output signal of the controller 20. By repeatedly performing this step, the same phase difference between the external clock and the internal clock is made.
At this time, assuming that a minimum delay time of the delay means 10 is defined as 1 step, the controller 20 cannot control a delay time below the 1 step. Also, assuming that a maximum delay time of the delay means 10 is defined as a max-delay, its magnitude determines the range of an operation frequency of the DLL circuit. That is, the operation of the DLL circuit is restricted by the magnitude of the max-delay. Owing to this reason, the conventional DLL circuit should increase the magnitude of the max-delay in order to reduce the magnitude of the 1 step and to increase an operation frequency range. As a result, an area occupied by the delay means 10 increases, thereby causing a problem to the effectiveness of the DLL circuit.